ASIC professionals
Advanced Clocking

Reliable interfacing between clock domains
Clock synchronization challenges
Resolution of flipflop metastability issues
Consistent multi-bit data
No missing samples/interrupts
Tailor-made exotic clock dividers
Glitch-free clock switches/ multiplexers
Clock cycle stealing

Advanced Clocking

Today’s SoC ASICs typically integrate a multitude of independent clock domains: high-speed crystals for active mode, RC oscillator or low-speed crystal for start-up and standby, RF VCOs, serial clocks received from an I2C or SPI host, etc. Under de hood of the SoC, data and signals will need to be exchanged across the boundaries of the various clock domains, e.g.:

  • A/D converter samples collected at a crystal clock, read by a host microcontroller through an SPI interface with its own independent serial clock originating from the host, the read transfers initiated by an asynchronous software thread
  • An interrupt signal set by hardware on a local (crystal) clock, read and cleared by a function or external microcontroller running on a different clock
  • A FIFO between two asynchronous processes running at different primary clocks

Without special provisions, there is a real danger of data being corrupted or lost due to clock synchronization issues:

  • When a signal changing on clock A is sampled on an independent clock B, metastability may occur in the sampling flipflop, resulting in an unpredictable and possibly unstable value, which may lead to corrupted data, or undesired or even illegal state transitions in finite state machines.



  • When a multi-bit signal changing on clock A is sampled on an independent clock B, even if metastability doesn’t occur or is properly addressed, the individual bits will experience different propagation delays, leading to inconsistent data when some bits get sampled just before they change while other bits get sampled just after the change. A byte changing from 127 to 128, for example, may get sampled as any value between 0 and 255.


  • When the availability of new data is signaled through a “new data available” handshaking or interrupt flag with a read-clear mechanism, and the arrival of new data coincides with the retrieval of previous data, the flag may fail to set or clear, resulting in loss or duplication of data.

For each sample, the risk of these issues actually occurring may be small, e.g. one in a million, but at today’s clock speeds (100 MHz ++), with an installed base of hundreds of millions of end products worldwide, and a tendency towards products being permanently ON for years without reset, even an epsilon chance becomes a very real problem, resulting in serious crashes, data loss or corruption, customer returns, dissatisfaction and a bad reputation of the product.
With more than 15 years of experience, PosEdge specializes in bullet-proof, tailor-made solutions for even the toughest clock synchronization challenges. We can analyze your design for clock synchronization hazards and recommend (and implement) adequate solutions such as:

  • Dedicated clock resynchronization logic, tailor-made to the task
  • “Dual port” flipflops that can be reliably set, cleared and read in 2 independent clock domains
  • Converting a multi-bit signal (e.g. an FSM state) to a different type of encoding that is insensitive to clock synchronization issues, such as Gray code
  • Ping/pong buffers or FIFOs

PosEdge also specializes in advanced manipulations of clock signals, such as:

  • Exotic (quadrature/programmable/fractional) clock dividers
  • “Any frequency” clock synthesis
  • Glitch-free clock switches/multiplexers
  • Clock cycle stealing, e.g. when all local oscillators are stopped in standby, and the external host sends an SPI command to wake up the function, the ASIC may actually steal a few cycles of the SPI clock from the host to run a boot sequence, then switch over to a local oscillator once it has started

Changing the clock frequency and clock source (internal RC versus external crystal) of an (embedded) microcontroller is a very effective way to dynamically reduce its power consumption at times when the software doesn’t need the processing power. A simple multiplexer may produce a glitch when changing from clock A to an independent clock B. When the glitch violates the minimum clock pulse width expected by the circuit behind it, timing is no longer met, and the circuit will function erratically and unpredictably. The Program Counter of the microcontroller may be incorrectly updated, derailing the software, manipulations on memory locations may be incorrectly executed, leading to corrupted memory contents and possibly illegal states…


Implementing a break-before-make mechanism under software control (disabling clock A first before enabling clock B) is not an option: after disabling clock A, the software will no longer receive a clock to execute the instruction to enable clock B. Therefore, dedicated, autonomous switch-over circuitry is required that is guaranteed to be free of any glitches. The design of such circuitry can be quite challenging, especially when it must accept a wide range of clock frequencies (e.g. if you cannot be sure that clock A is always slower than clock B).


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