ASIC design automation
ASIC Tools

Sophisticated tools for ASIC design

Save time, reduce costs and eliminate human error
Provided free of charge as a courtesy to the ASIC designer community


ASIC Tools

PosEdge’s philosophy is that any tedious, recurring task that can be done by a machine should be done by a machine. We invest heavily in the development of fully automated tools and scripts that reduce time-consuming tasks to a single push of a button. This allows us to keep costs down for our clients, free up our human resources for more intellectual tasks and eliminate human error in the process.

As a courtesy to our fellow ASIC designers, PosEdge has decided to make its tools available in the public domain, free of charge, for any use, including commercial use, and the right to redistribute them. Modifications are prohibited. Usage is at your own risk; due to the freeware nature of these materials, we cannot accept liability for any damages resulting from (improper) use of or any bugs or inconsistencies in the materials.


Ultra-wide dynamic range current shunt, 50nA - 5A without range switching or changing shunts

Also struggling to reliably measure the (average) current consumption of your energy harvesting HW, ASIC, microcontroller or RF transceiver with sub-uA standby current but tens or hundreds of mA active current?
Check out the revolutionary new type of current shunt that we have invented, completely abandoning the traditional resistive shunt, replacing it by a switched capacitor :

https://www.kickstarter.com/projects/2140604734/wide-dynamic-range-current-voltage-and-power-facto?ref=email
Turns your PC into an ultra-wide range current/volt/power (factor) meter/oscilloscope/datalogger, USB powered, 2.5kV


CIC filter frequency response explorer

http://www.at1x.nl/downloads/CIC/CIC.zip


Halfband filter designer and optimizer

http://www.at1x.nl/downloads/halfband/halfband.zip


FIR filter complexity calculator

Accurately predicts the area and power consumption of a FIR filter.

The tools perform very sophisticated domain conversions, polyphase and decomposition algorithms (CSD, common subexpression identification, constant bit identification, constant propagation, bitwidth pruning, minimum spanning adder tree design, and a couple of proprietary techniques) to achieve the best possible implementation.

http://www.at1x.nl/downloads/FIRcomplexity/FIRcomplexity.zip


FIR filter explorer and optimization tool

Explore the frequency response of a FIR filter and optimize its coefficients for area, power consumption, performance (ripple, attenuation)

The tools perform very sophisticated domain conversions, polyphase and decomposition algorithms (CSD, common subexpression identification, constant bit identification, constant propagation, bitwidth pruning, minimum spanning adder tree design, and a couple of proprietary techniques) to achieve the best possible implementation.

http://www.at1x.nl/downloads/FIRoptim/FIRoptim.zip


FIR filter Verilog generator

Automatically generates a Verilog RTL implementation of a given FIR filter.

The tools perform very sophisticated domain conversions, polyphase and decomposition algorithms (CSD, common subexpression identification, constant bit identification, constant propagation, bitwidth pruning, minimum spanning adder tree design, and a couple of proprietary techniques) to achieve the best possible implementation.

http://www.at1x.nl/downloads/FIR2Verilog/FIR2Verilog.zip


Binary file editor, viewer and 2-way or 3-way comparison

http://www.at1x.nl/downloads/bincompare/bincompare.zip


Short Hand Verilog Initiative

RTL coding follows the 80/20 rule : 20% is creative, challenging, and therefore fun, 80% is tedious, meticulous and downright boring : adding a new signal to the interface of a submodule burried in the hierarchy and bringing it to top level, changing names or dimensions of signals throughout the hierarchy, having to propagate clocks and resets and specify "reg"s in order to add some sequential elements etc. Or just think of the effort it takes to make your RTL code cosmetically pleasing and easy to read...

This is why we have started the Short Hand Verilog initiative, that will allow for quick-and-dirty RTL coding and aims to reduce the boring overhead to a minimum. A preprocessor will take your Short Hand Verilog (.shv) source files and automatically convert them to ordinary Verilog, layouted in a cosmetically pleasing style, and syntactically 100% flawless.

Quick-and-dirty may sound risky, but we actually intend to eliminate the human error as much as possible. Verilog itself has some notorious pitfalls, because the language is actually too rich for RTL coding, it will allow for syntactically correct constructs that cannot be properly translated to hardware (unintentionally inferred latches, incomplete case statements, etc.). Short Hand Verilog will be a language strictly dedicated for RTL coding, and will therefore not allow for unsynthesizable code.

We would like to gather some feedback from the ASIC designers community, do you like our initiative, do you have some ideas/recommendations what features we should include, do you want to get involved?

When finished, the language specifications and preprocessor tools will be made available here, free of charge.


More downloads will be added soon!

 

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