We develop automated tools and scripts alongside our IP to reduce repetitive design work, improve efficiency and eliminate human error. These tools underpin our ongoing IP development.
As a courtesy to our fellow ASIC designers, PosEdge has decided to make its tools available in the public domain, free of charge, for any use, including commercial use, and the right to redistribute them. Modifications are prohibited. Usage is at your own risk; due to the freeware nature of these materials, we cannot accept liability for any damages resulting from (improper) use of or any bugs or inconsistencies in the materials.
CIC filter frequency response explorer
Halfband filter designer and optimizer
FIR filter complexity calculator
Accurately predicts the area and power consumption of a FIR filter.
The tools perform very sophisticated domain conversions, polyphase and decomposition algorithms (CSD, common subexpression identification, constant bit identification, constant propagation, bitwidth pruning, minimum spanning adder tree design, and a couple of proprietary techniques) to achieve the best possible implementation.
FIR filter explorer and optimization tool
Explore the frequency response of a FIR filter and optimize its coefficients for area, power consumption, performance (ripple, attenuation)
The tools perform very sophisticated domain conversions, polyphase and decomposition algorithms (CSD, common subexpression identification, constant bit identification, constant propagation, bitwidth pruning, minimum spanning adder tree design, and a couple of proprietary techniques) to achieve the best possible implementation.
FIR filter Verilog generator
Automatically generates a Verilog RTL implementation of a given FIR filter.
The tools perform very sophisticated domain conversions, polyphase and decomposition algorithms (CSD, common subexpression identification, constant bit identification, constant propagation, bitwidth pruning, minimum spanning adder tree design, and a couple of proprietary techniques) to achieve the best possible implementation.
Binary file editor, viewer and 2-way or 3-way comparison
Short Hand Verilog Initiative
RTL coding follows the 80/20 rule : 20% is creative, challenging, and therefore fun, 80% is tedious, meticulous and downright boring : adding a new signal to the interface of a submodule burried in the hierarchy and bringing it to top level, changing names or dimensions of signals throughout the hierarchy, having to propagate clocks and resets and specify "reg"s in order to add some sequential elements etc. Or just think of the effort it takes to make your RTL code cosmetically pleasing and easy to read...
This is why we have started the Short Hand Verilog initiative, that will allow for quick-and-dirty RTL coding and aims to reduce the boring overhead to a minimum. A preprocessor will take your Short Hand Verilog (.shv) source files and automatically convert them to ordinary Verilog, layouted in a cosmetically pleasing style, and syntactically 100% flawless.
Quick-and-dirty may sound risky, but we actually intend to eliminate the human error as much as possible. Verilog itself has some notorious pitfalls, because the language is actually too rich for RTL coding, it will allow for syntactically correct constructs that cannot be properly translated to hardware (unintentionally inferred latches, incomplete case statements, etc.). Short Hand Verilog will be a language strictly dedicated for RTL coding, and will therefore not allow for unsynthesizable code.
We would like to gather some feedback from the ASIC designers community, do you like our initiative, do you have some ideas/recommendations what features we should include, do you want to get involved?
When finished, the language specifications and preprocessor tools will be made available here, free of charge.